Daniel Herrera and Barend van Liepmd
PROCEEDINGS OF THE EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN 978 (2010)
Analog VLSI circuits are being used successfully
to implement Artificial Neural Networks (ANNs). These analog
circuits exhibit nonlinear transfer function characteristics
and suffer from device mismatches, degrading network
performance. Because of the high cost involved with analog
VLSI production, it is beneficial to predict implementation
performance during design.
We present an FPGA-based accelerator for the emulation
of large (500+ synapses, 10k+ test samples) single-neuron
ANNs implemented in analog VLSI. We used hardware timemultiplexing
to scale network size and maximize hardware
usage. An on-chip CPU controls the data flow through various
memory systems to allow for large test sequences.
We show that Block-RAM availability is the main implementation
bottleneck and that a trade-off arises between emulation
speed and hardware resources. However, we can emulate large
amounts of synapses on an FPGA with limited resources.