IEEE TRANSACTIONS ON NEURAL NETWORKS 22, 7 (2011)
Analog VLSI implementations of neural networks can compute using a fraction of the size and power required by their digital counterparts. However, intrinsic limitations of analog hardware such as device mismatch, charge leakage, and noise, reduce the accuracy of analog arithmetic circuits, degrading the performance of large-scale adaptive systems. In this paper, we present a detailed mathematical analysis which relates different parameters of the hardware limitations to specific effects on the convergence properties of linear perceptrons trained with the Least-Mean-Square (LMS) algorithm. Using this analysis, we derive design guidelines and introduce simple on-chip calibration techniques to improve the accuracy of analog neural networks with a small cost in die area and power dissipation. We validate our analysis by evaluating the performance of a mixed-signal CMOS implementation of a 32-input perceptron trained with LMS.